Graphene is a single layer of graphite. Graphene possesses extraordinary electronic properties. For example, the electron carriers in graphene exhibit very high mobilities that are attractive for high-performance radio frequency (rf) circuits. One major challenge in utilizing devices and complex circuits involving graphene is the incompatibility of the growth conditions of graphene and the process limitation of current complementary metal-oxide semiconductor (CMOS) technology. For example, graphene layers grown epitaxially from silicon carbide (SiC) substrates require a reaction temperature of at least 1,200 degrees Celsius (° C.), which greatly exceeds the temperature cap of from about 350° C. to about 400° C. for CMOS processes. One way to obtain graphene sheets at lower temperatures is achieved by mechanical exfoliation of bulk graphite and the transfer to suitable substrates. Nevertheless, during the subsequent processes, graphene obtained from either approach may be destroyed via oxidation and the properties of the graphene may also be altered.
Due to its high carrier mobility, graphene is an attractive material as the active component in rf circuit applications. For rf circuits, the performance of a transistor is mainly determined by the cut-off frequency, i.e., the frequency at which the current gain of the transistor becomes unity. In order to improve the cut-off frequency of a transistor, it is necessary to minimize the parasitic capacitance and residual resistance associated with contacts and interconnects of the transistor.
In general, a field effect transistor (FET) includes a source, a drain and a channel(s) connecting the source and the drain. A gate, separated from the channel by a dielectric, regulates electron flow through the channel. Metal contacts (electrodes) are typically provided to the source, drain and gate. With conventional graphene-based FETs, two types of gate structures are usually adopted. In the first type, the gate contact overlaps with the source/drain metal contacts to ensure good gate control. In the second type, the gate underlaps the source/drain contacts to avoid the parasitic capacitance between the gate and the source/drain contacts. In the first design, device performance suffers from the significant parasitic capacitance due to the contact overlap. In the second design, the ungated region between the gate and the source/drain contacts contributes to the residual series resistance. Either design fails to address the issue of parasitic capacitance and residual series resistance simultaneously for high performance operation.
Therefore a new fabrication scheme that effectively combines existing CMOS technology and graphene, so as to permit the successful use of graphene as the active or passive element in practical devices and/or circuits, would be desirable, as would graphene-based transistor device designs that minimize both parasitic capacitance and residual series resistance.